The present invention relates generally to the field of semiconductor device manufacturing, and more specifically to a method for aligning a projected photolithography mask pattern image with respect to the underlying device layer.
The manufacture of complex semiconductor devices involves printing multiple layers of device features onto a substrate using photolithography printing techniques. To achieve proper electrical contact between the different layers or levels of device features, each layer must be accurately aligned with the previous underlying layer. Misalignment of a layer of device features with respect to the previous underlying layer may result in unintended opens or shorts between device features on different levels, causing loss of the entire product.
Alignment of layers of device features has conventionally been achieved through the use of overlay targets, typically box-in-box targets, located in the kerf surrounding the outer edge of a chip product area on a semiconductor wafer. FIG. 1A shows a schematic view of a chip product area 100 on a semiconductor wafer. The chip product area is also referred to as the product xe2x80x9cfieldxe2x80x9d on the wafer. Box-in-box overlay targets 111-114 are located in the kerf surrounding product field 100. Typically, four box-in-box overlay targets are positioned as shown. The relative position of notch 120 on the semiconductor wafer is also shown.
Photolithography printing involves the deposition of a layer of photosensitive material on a semiconductor substrate, exposure of the photosensitive material through a mask, and development of the exposed photosensitive layer. Exposure is typically carried out in a scanner or stepper tool, wherein an exposure slit is passed across the surface of the substrate, thereby sequentially exposing narrow strips of the photosensitive layer. FIG. 1A schematically shows scanner exposure slit 130, and the direction of its movement relative to product field 100, box-in-box targets 111-114, and notch 120.
Product field 100 may comprise many device features, some of which are shown schematically in FIG 1B. For example, a lower layer may comprise connectors 101, and an upper layer may comprise line 102. Features 101 may be referred to as Level 1 features, and feature 102 may be referred to as a Level 2 feature. Proper alignment of the projected Level 2 photolithography mask image relative to the underlying Level 1 is critical. If line 102 is positioned too far to the right or left in the x direction, this feature may overlie the wrong contacts 101. If line 102 is positioned too far up or down in the y direction, this feature may not touch one of the intended contacts 101. A small amount of alignment error can be tolerated, depending on the relative size of the features to be printed. This amount of tolerable alignment error may be referred to as the overlay budget. However, as typical device feature sizes continue to shrink, errors in alignment of these layers must be reduced accordingly.
As stated previously, a layer to be printed on a semiconductor substrate has conventionally been aligned with the previously printed layer through the use of box-in-box targets, such as targets 111-114 shown in FIG. 1A. The larger box is typically printed in the kerf of the underlying layer, and the smaller box is associated with the next layer to be printed. The center of the smaller box is aligned such that it directly overlays the center of the larger box. In other words, the overlay error or offset between the center of each smaller (target) box and the center of the corresponding larger box is driven to zero. Once each box-in-box target is properly aligned, it is assumed that the device features within the product field will also be properly aligned.
However, it has been observed that significant overlay errors can occur within the product field even when the box-in-box target overlay error is driven to zero. This phenomenon may be the result of lens aberrations (e.g., distortions and coma induced pattern displacements) and other tool anomalies that cause features within the product field to be misaligned. In particular, exposing different product layers using different tools with mismatched lens distortion patterns can often result in significant within field overlay registration errors. Similarly, exposing different product layers using the same tool, but using different lens illumination conditions, can also lead to significant within field overlay registration errors. Therefore, overlay error measured at the box-in-box targets is not a true indication of the overlay error within the product field.
This problem of overlay error due to lens aberrations and other causes exists with virtually all exposure tools. Tools having similar lens distortion patterns could be used together in the manufacture of semiconductor chips, thereby reducing the tool-to-tool overlay error, and tools whose lens distortion patterns are grossly mismatched could be avoided. Likewise, changes in lens illumination conditions within a single tool between exposure of successive product layers could be avoided. Alternatively, different tools could be dedicated for critical product layers or levels.
However, all of these techniques suffer from the disadvantage of reduced flexibility in manufacturing tool usage. Using tools only in matched pairs reduces flexibility in that when one tool is down for servicing or maintenance, the other tool is therefore not usable. Similarly, avoiding changes in lens illumination conditions within a single tool limits flexibility in the performance of tool servicing or maintenance. Finally, dedicating particular tools for critical product layers or levels would require a different tool for each successive exposure, resulting in a prohibitively large and expensive manufacturing facility.
Therefore, there is a need in the art for a method of aligning two or more product layers, wherein the method does not rely on the assumption that minimizing overlay error in the box-in-box targets results in minimized overlay error within the product field.
In addition, there is a need in the art for a method of optimizing the alignment of two or more product layers, wherein the method does not require that the lens distortion signatures used in successive exposures be matched.
The present invention eliminates the aforementioned problems by measuring the overlay error of product features within the product field, determining an adjustment factor based on this overlay error, and applying the adjustment factor to the box-in-box targets to obtain nonzero box-in-box target offsets and to minimize within field overlay error.
A method for aligning a projected image of a photolithography mask pattern for a second product layer with respect to a first product layer is disclosed. The first product layer includes a periphery surrounding a first product area, the mask pattern for the second product layer includes a periphery surrounding a second product area, the first product area includes at least one first product feature, and the second product area includes at least one second product feature. The method comprises the steps of: (a) providing at least one first reference feature in the periphery of the first layer; (b) providing at least one second reference feature in the periphery of the mask pattern for the second product layer; (c) measuring a first overlay error between the at least one first reference feature and the projected image of the at least one second reference feature; (d) measuring a second overlay error between the at least one first product feature and the projected image of the at least one second product feature; (e) determining at least one adjustment factor to be applied to the first overlay error between said reference features, such that said adjustment factor minimizes the second overlay error between said product features; and (f) applying said at least one adjustment factor to the first overlay error between said reference features.